1. Field of the Invention
This invention relates to, for example, a nonvolatile semiconductor memory device, and more particularly to a semiconductor memory device with a reference potential generator for generating a reference potential.
2. Description of the Related Art
FIG. 5 is a schematic circuit diagram of a nonvolatile semiconductor memory, such as an EPROM (Erasable Programmable ROM). A memory cell MC contains a floating gate FG and a control gate CG. Memory cells MC of this type are arranged in a matrix. The control gates CG of the individual memory cells MC are connected to word lines WL1, WL2, . . . , their sources are connected to a power supply Vs, and their drains are connected to bit lines BL1, BL2 . . . The individual bit lines BL1, BL2 . . . are connected to a power supply Vcc via a select transistor (not shown) and a resistor R1, as well as to one input terminal of a sense amplifier S/A.
Connected to the other input terminal of the sense amplifier S/A is a reference potential generator circuit RPG composed of a dummy cell DMC and a resistor R2. The dummy cell DMC has the same structure as that of the memory cell MC, and its drain is connected to the other input terminal of the sense amplifier S/A. One terminal of the resistor R2 is connected to the other input terminal of the sense amplifier S/A, and the other terminal of resistor R2 is connected to power supply Vcc. The resistance of the resistor R2 is set at half of the resistance of resistor R1. The potential on the bit line may be either at a high level where "0" data is written into a memory cell, preventing a cell current from flowing, or at a low level where no "0" is written in a memory cell, permitting a cell current to flow. In the reference potential generator circuit RPG, the dummy cell DMC and resistor R2 generate an intermediate potential between the high-level and the low level bit-line potential as a reference potential. The sense amplifier S/A senses data by comparing a bit-line potential with the reference potential according to the data stored in the memory cell selected.
The source and drain of the memory cell are formed by implanting ionized impurities into a substrate SB using a gate electrode G including the control gate CG and floating gate FG as a mask. However, it is difficult to implant ions at right angles with all of the memory cells because of the structure of the ion-implantation machine. In the case of some types of ions, to prevent channeling, ions may be implanted at a specified angle. During ion implantation, when the implantation angle is not at right angles to the substrate SB, shadowing will take place due to the gate electrode G. This makes the source S and drain D formed on both sides of the gate electrode G asymmetrical with respect to the gate electrode G, making the source S and drain D different in size from each other. As a result, the memory cells connected to the word lines in the odd-numbered rows differ from those connected to the word lines in the even-numbered rows in the equivalent circuit, resulting in the difference in cell current between them. Therefore, when a memory cell in which no data is written is selected, the cell current differs, depending on whether the memory cell is connected to a word line in an odd-numbered row or in an even-numbered row.
The reference potential is generated by one dummy cell DMC and resistor R2 as mentioned earlier, and is determined by the characteristics of the dummy cell DMC. Since the dummy cell DMC is formed through the same manufacturing processes as those of memory cells, it has the same configuration as that of the memory cells connected to the word line in the odd-numbered row or in the even-numbered row as described above. Therefore, in sensing data, the dummy cell DMC was able to give a suitable reference potential to either the memory cells connected to a word line in an odd-numbered row or the memory cells connected to a word line in an even-numbered row, but was unable to give a suitable reference potential to the other memory cells. As a result, the sense amplifier S/A was unable to sense the potential on the bit line accurately.